4 Take-Aways from Huawei’s Atlas 960E SuperPoD Launch (Tech Strategy)

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The Huawei Connect conference just happened in Shanghai.

And this is just about my favorite conference in China. It’s the one for developers and there are deep dives into all the new capabilities.

The big management announcement this was for the Atlas 960E SuperPoD, which is the centerpiece of Huawei’s new Peerium Computing Architecture.

Which brings me to the first take-away.

Take Away 1: The SuperPod 960E Is Huawei Completely Rebuilding AI Infrastructure. At Scale.

“Peerium” is a strange term.

What they are trying to describe (I think) is a computing architecture where every GPU / NPU is a “peer” to every other GPU / NPU. And every GPU/NPU connects to every other one.

That’s a guess.

This is about both scaling up and integrating the AI compute. It’s why the SuperPoD operates as one gigantic, integrated computer.

And Huawei is definitely thinking about scale in AI infrastructure. They are talking about AI infrastructure that can handle 10T parameter models. And maybe even 100T parameter models.

The new Atlas SuperPoD 960E has 4,096 NPUs.

And you can put them together into a SuperCluster (that’s a good name) with +500,000 NPUs.

And the main selling points of the new Atlas SuperPoD are:

  • High-performance inference and training.
  • Ultra-high bandwidth.
  • Ultra-low latency. From 40ms to 10ms.
  • Unified memory addressing.
  • Flexible scaling.

And all of the problems become more important as you move to agentic. Here’s a slide from Seaway Zhang’s talk on the Atlas 950 in January.

The 960E an upgrade from the 950, which I wrote about in January. And from the CloudMatrix 384, which I wrote about last year.

Which brings me to the next term, which is “Nested BSP”.

To get all those NPUs to work together as peers, you need large scale parallel compute that can work seamlessly, without lags and latency. For this, the SuperPod uses Nested BSP (Nested Bulk Synchronous Parallel).

We’re seeing an interesting shift away from traditional computing paradigms with its classic single-machine von Neumann architecture.

Peerium (at scale) also requires really good performance in peer interconnect and unified memory addressing. More on those below.

So, we’re seeing a rebuilding of AI infrastructure from top to bottom.

Take Away 2: Ascend GPUs Are Advancing Rapidly Across the Board.

Huawei didn’t release any new chips at this event. But they did lay out the Ascend chip roadmap.

They announced that development for the next generation Ascend 960 chip is ahead of schedule. And is split into two specialized variants rather than a single general chip. There is:

  • Ascend 960DT: A training-focused variant that was moved up to launch in Q1 2027.
  • Ascend 960PR: An inference-focused variant moved up to arrive in Q3 2027.

Recall, Huawei recently announced their new quasi-three-dimensional chip design. They called their new design LogicFolding, which benefits from “Tau scaling”. And this has now moved into commercialization. The recently released trifold uses this chip design. I don’t think the SuperPoD servers use it (yet).

So, we can see progress across the board in chips.

However, compute performance also heavily relies on memory and interconnect.

Which brings me to my next point.

Take-Away 3: Huawei is the King of Interconnect

The Peerium Computing Architecture is a strategic response to Huawei not having access to more powerful NVIDIA GPUs. As mentioned, they are advancing their own chips rapidly. But their cool move is the attempt to leapfrog to frontier level performance with clever architecture. That’s “peerium”, which is about putting a lot of their still less powerful chips together and getting them to work together effectively.

But this requires advancements in interconnection. To get 5000 NPUs to work as one computer, you need the peer-to-peer chips to communicate really fast and super-efficiently.

These AI data centers are integrated computers. And as you add more NPUs, how the NPUs connect to each other really matters. You can’t just keep expanding horizontally, with lots of additional routers and switches. Larger architectures mean more hierarchy, more delays and a larger physical space.

And this problem becomes more challenging when you have 14x the number of NPUs as NVIDIA. For example:

  • NVIDIA has 576 GPUs in 1-8 cabinets.
  • Huawei’s SuperPoD 950 has 8,192 NPUs in 160 cabinets.

For Huawei, that means:

  • UnifiedBus (UB)
  • Their new Hi-ONE optical engine, which was announced this week.

Enter Huawei’s proprietary UnifiedBus (also known as “Lingqu”) optical interconnect, which I’ve written about before.

Huawei’s UnifiedBus is designed to keep thousands of less-powerful chips in perfect sync across a giant room, overcoming physical distance and traditional data center bottlenecks.

UnifiedBus (UB) is a single, unified interconnect protocol designed to replace multiple older, separate networking layers. While traditional data centers use one technology for talking (Ethernet/InfiniBand) and another for sharing memory (PCIe), Huawei’s UnifiedBus merges them into one optical fabric.

UnifiedBus (UB) Is Huawei’s Chip-to-Chip “Nervous System”

In a normal data center, if Chip A in one cabinet needs to talk to Chip B in another cabinet, the data has to be packaged into a network format (like TCP/IP), sent through a switch, and unpacked at the other end. This creates a delay (i.e., latency).

  • Huawei’s UnifiedBus removes the packaging step. It uses a peer-to-peer mesh where any chip can talk to any other chip directly. This is high-speed, peer-to-peer communication between NPUs. Instead of data traveling through several stops (CPU, Network Card, Switch), UnifiedBus creates a direct path.
  • And this achieves 2-microsecond latency across a room the size of two basketball courts. This is fast enough for the 8,192 chips to stay in perfect sync during complex AI training.

Hi-ONE Is Huawei’s New Upgraded Optical Engine

This was one of their big announcements.

Hi-ONE stands for High-Density Optical-Interconnect-Node Engine, which is Huawei’s proprietary optical interconnect product based on Near-Packaged Optics (NPO).

Hi-ONE is an upgrade from traditional NPOs and light modules in three ways:

  • It has its own built-in light source. Standard Near-Packaged Optics (NPO) NPO architectures place the laser into an External Laser Source (ELS) away from the main compute/optics substrate to avoid thermal and reliability issues. Huawei’s Hi-ONE engine incorporates the light source directly inside the optical engine.
  • It is much closer to the GPUs. Hence the term near packaged optics (NPO).
  • It is multi-channel. It can run lots of connections together. You replace lots of smaller optical modules.

And the Atlas 960E is the first SuperPoD to deploy such an NPO in mass production. That means:

  • 5,500 Hi-ONE units replace +48,000 traditional pluggable optical modules.
  • Less power consumption. There are far fewer modules.
  • A doubling of fault-free operating time. There are far fewer modules.
  • Transmission capacity increases to 7.2 Tbit/s per single engine. This is because you have moved modules much closer to the GPUs, you have reduced the use of copper and you have removed lots of interchange points.

Take-Away 4: Huawei is Expanding Memory Pooling and KV Cache. From Chip to DRAM to SSD.

For peerium to work, you also need advances in memory.

I think this is the topic that doesn’t get enough attention. Everyone talks about the Atlas SuperPoD, but nobody talks about OceanStor.

In previous articles, I wrote about how the UnifiedBus creates a “shared brain”.

The system treats the memory attached to all chips as one single, big 1.1 Petabyte memory pool. To the software, it doesn’t look like a network transfer; it looks like the chip is just talking to its own local RAM.

One benefit is that developers don’t have to manually tell the system to “send data from Chip 1 to Chip 500.” They simply tell the software to “store this data,” and the system handles it across the entire pool. It behaves like one giant computer with a 1.1 PB hard drive that is as fast as local RAM.

In this new peerium AI architecture, memory and storage are particularly important in two places:

High-Speed Compute Needs Lots of Memory

In an Atlas 960E SuperPoD, the compute tier has up to one petabyte of High-Bandwidth Memory (HBM) that is attached to the NPUs. This is to support heavy real-time matrix operations and model training.

But you also need tons of memory available for the KV cache. Especially as you move from AI to agents, you get exploding context. And therefore, greater increased memory requirements.

Context Storage Also Needs Lots of Memory

In the OceanStor M900, ultra-long context and multi-turn AI agent inference create big memory requirements. They solve this with a multi-tiered Key Value (KV) cache.

It expands the KV cache beyond on-chip memory and standard DRAM. It expands to high-performance SSD layers.  This means a single cluster expands to 64 petabytes of capacity. And available cache per NPU increases from gigabytes to terabytes.

Of course, this approach to multi-tiered memory requires really fast interconnect. Which is why the UnifiedBUS and the NPO are so important.

***

Ok. That’s it. Overall, it’s pretty cool.

Jeff

*Disclosure: AsiaTech Services, LLC has had a paid commercial relationship with Huawei within the past 12 months. This article received no financial sponsorship or backing.*

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From the Concept Library, concepts for this article are:

  • AI Cloud
  • AI Infrastructure and Data Centers

From the Company Library, companies for this article are:

  • Huawei

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